SPD module chip data
General description of the SPD standard: JEDEC Standard No. 21-C, 4.1.2 - SERIAL PRESENCE DETECT STANDARD, General Standard.
Description of the DDR2 SPD standard: JEDEC Standard No. 21-C, 4.1.2.10 - Appendix X: Specific SPDs for DDR2 SDRAM (Revision 1.2).
| Parameter |
Byte |
Value |
Interpretation |
| Fundamental Memory Type |
2 |
08h |
DDR2 SDRAM |
| Number of Row Addresses on this assembly |
3 |
0Eh |
14 (RA0-RA13) |
| Number of Column Addresses on this assembly |
4 |
0Ah |
10 (CA0-CA9) |
| Number of DIMM Banks |
5 |
61h |
2 physical banks |
| Data Width of this assembly |
6 |
40h |
64 bit |
| Voltage Interface Level of this assembly |
8 |
05h |
SSTL 1.8V |
| SDRAM Cycle time (tCK) at maximum supported CAS# latency (CL X) |
9 |
25h |
2.50 ns (400 MHz) |
| DIMM configuration type |
11 |
00h |
Non-ECC |
| Refresh Rate/Type |
12 |
82h |
7.8125 ms - 0.5x reduced self-refresh |
| Primary SDRAM Width (organization type) of the memory module chips |
13 |
08h |
x8 |
| Error Checking SDRAM Width (organization type) of the memory chips in the ECC module |
14 |
00h |
Not defined |
| Burst Lengths Supported (BL) |
16 |
0Ch |
BL = 4, 8 |
| Number of Banks on SDRAM Device |
17 |
08h |
8 |
| CAS Latency (CL) |
18 |
30h |
CL = 5, 4 |
| Minimum clock cycle (tCK) at reduced CAS# latency (CL X-1) |
23 |
37h |
3.7 ns (270.3 MHz) |
| Minimum clock cycle (tCK) at reduced CAS# latency (CL X-2) |
25 |
00h |
Not defined |
| Minimum Row Precharge Time (tRP) |
27 |
32h |
12.5 ns
5, CL = 5
4, CL = 4 |
| Minimum Row Active to Row Active delay (tRRD) |
28 |
1Eh |
7.5 ns
3, CL = 5
2, CL = 4 |
| Minimum RAS to CAS delay (tRCD) |
29 |
32h |
12.5 ns
5, CL = 5
4, CL = 4 |
| Minimum Active to Precharge Time (tRAS) |
30 |
2Dh |
45.0 ns
18, CL = 5
12, CL = 4 |
| Module Bank Density |
31 |
01h |
1024 MB |
| Write recovery time (tWR) |
36 |
3Ch |
15.0 ns
6, CL = 5
4, CL = 4 |
| Internal WRITE to READ command delay (tWTR) |
37 |
1Eh |
7.5 ns
3, CL = 5
2, CL = 4 |
| Internal READ to PRECHARGE command delay (tRTP) |
38 |
1Eh |
7.5 ns
3, CL = 5
2, CL = 4 |
| SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) |
41, 40 |
39h, 06h |
57.0 ns
23, CL = 5
16, CL = 4 |
| SDRAM Device Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) |
42, 40 |
7Fh, 06h |
127.0 ns
51, CL = 5
35, CL = 4 |
| Maximum device cycle time (tCKmax) |
43 |
80h |
8.0 ns |
| SPD Revision |
62 |
12h |
Revision 1.2 |
| Checksum for Bytes 0-62 |
63 |
0Dh |
13 (true) |
| Manufacturer's JEDEC ID Code |
64-71 |
7Fh, 7Fh, 9Eh |
Corsair |
| Module Part Number |
73-90 |
- |
CM2X2048-9136C5D |
| Module Manufacturing Date |
93-94 |
08h, 0Ch |
Year 2008, Week 12 |
| Module Serial Number |
95-98 |
00h, 00h,
00h, 00h |
Not defined |
Two CAS# latencies are supported by SPD - 5 and 4. The first value (CL X = 5) corresponds to DDR2-800 (2.5 ns cycle time, 400 MHz) with 5-5-5-18 timings (exact values). The second CAS latency value (CL X-1 = 4) corresponds to non-standard DDR2-540 (3.7 ns cycle time, 270.3 MHz) with integer timings (4-4-4-12). But you will hardly want to reduce memory frequency that much to use hardcore timings.
SPD revision and checksum are specified correctly. Manufacturer's ID Code is also available. But there is no Serial Number. And the part number of the module corresponds to what's printed on the modules.
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